Functional Verification Jobs

technical development at various sub-contractors. * Support development of associated verification and test plans to validate performance requirements. * Must ... software delivery/deployment process * Experience with project management and leading cross-functional teams to ensure project completion. PDM/PLM experience and requirements ... More

world-wide architecture and modeling team to develop functional models for various next-generation test-chip and product solutions. Primary responsibilities include generating ... as well as generating cycle accurate models for use in verification. Job Functions include: Developing a generic modeling framework that ... More

for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which ... synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout ... More

for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which ... synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout ... More

for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which ... synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout ... More

for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which ... synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout ... More

for 1. full chip activities covering floorplanning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities which ... synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout ... More

: Xilinx, Altera, Mentor, Synopsys Block / SoC level functional verification in Verilog / vhdl / SystemVerilog Emulation or FPGA ... PCIe DDR2, DDR3, I2C , GPIOFPGA Emulation Porting ASIC RTL on FPGA RTL verification System Debug of hw, fw, FPGA ... More

verification strategy for the Graphics chips Specifying an overall design verification plan for full chip SoC Specifying or reviewing verification ... Experience with coverage-based verification methodology Experience in writing testplans and testcases Excellent debug skills in both functional and gate level ... More

verification strategy for the Graphics chips Specifying an overall design verification plan for full chip SoC Specifying or reviewing verification ... Experience with coverage-based verification methodology Experience in writing testplans and testcases Excellent debug skills in both functional and gate level ... More