Advanced Micro Devices Jobs

Responsibilities: The position is for a Physical Design Engineer in the AMD PD group catering to building the next generation ... of the chip from RTL/gates to tapeout. The Physical Design Engineer will be responsible for 1. full chip activities covering ... More

Key Responsibilities: The position is for a Physical Design Engineer in the AMD PD group catering to building the next ... of the chip from RTL/gates to tapeout. The Physical Design Engineer will be responsible for 1. full chip activities covering ... More

Key Responsibilities: The position is for a Physical Design Engineer in the AMD PD group catering to building the next ... of the chip from RTL/gates to tapeout. The Physical Design Engineer will be responsible for 1. full chip activities covering ... More

Key Responsibilities: The position is for a Physical Design Engineer in the AMD PD group catering to building the next ... of the chip from RTL/gates to tapeout. The Physical Design Engineer will be responsible for 1. full chip activities covering ... More

The position is for a Physical Design Engineer in the AMD PD group catering to building the next generation fusion ... of the chip from RTL/gates to tapeout. The Physical Design Engineer will be responsible for 1. full chip activities covering ... More

PMP certification is a plus, but not mandatory Software product project/program management experience is desired Key Responsibilities: Run complex projects/programs ... and driving cross functional activities Define resources and schedule for project/program implementation Manage horizontally across several functional organizations locally and ... More

Designer Engineer 2: Verification Requirements Key Responsibilities: Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification ... ASIC Design Verification Experience in Graphics or Multimedia domains is a plus Must have excellent knowledge of ASIC Design Flow ... More

with subsystem/SOC and Physical design teams to resolve constraints, floorplan, area and power parameters. Design manager is responsible to work closely with the IP teams, align with SOC RTL/Netlist schedules, conduct design reviews ... More

MTS Designer Engineer: Implementation: Job Description The candidate will be responsible for participating in the pre-silicon block and system level design. ... More

MTS Designer Engineer: Verification Requirements Key Responsibilities: Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification ... ASIC Design Verification Experience in Graphics or Multimedia domains is a plus Must have excellent knowledge of ASIC Design Flow ... More